1. Field of the Invention
This invention relates to clock feeding circuitry in an integrated circuit, and a method for adjusting clock skew in such integrated circuits, especially in semi-custom-made LSI's with interconnections designed by users, namely, in sea-of-gates type LSI's.
2. Description of the Related Art
In a clock feeding circuit for feeding clock pulses to activate logic circuits on an IC chip, differences of delay time, that is, clock skew, of the clock pulses input to logic circuits, may occur between the logic circuits. This is because lengths of interconnection routes from inputs of the clock feeding circuit to the respective logic circuits, and loads of such circuits, may differ.
In order to reduce the clock skew, circuits for distributing clock pulses as described in Japanese Patent Unexamined Publication No. Hei 1-157,115 (dated Jun. 20, 1989) and the copending application for United States patent of applicants assignee, Ser. No. 933,345 (filed Aug. 8, 1992), have been proposed. The former construction includes a plurality of regions in which logic circuits exist, and a clock pulse feeder provided at a position central to the regions, so as to equalize the lengths of the interconnection routes from the feeder to the logic circuits to which the clock pulse is finally fed. The latter construction, which is described herein for purposes of comparison with the invention and does not constitute legal prior art, includes the clock pulse feeder nearly at a center of the layout of the logic circuits. Major branches of the interconnection routes have a broad width, and terminal branches are connected between the major branch and the logic circuits. In this construction, the major branches extend in a vertical direction of a region designed by the user, hereinafter identified as a "user-designed region", and the terminal branches extend in a horizontal direction from the major branch. Each terminal branch connects to almost the same number of logic circuits with almost the same wiring length, so that lengths of the interconnection routes from the clock feeder to each of the logic circuits to which the clock pulse is finally fed, and loads of the circuits, are almost the same.
As the scale of the circuit is increased, however, the problems to be solved by the layout design become more complex, and therefore, it is more difficult to reach optimum solutions. Accordingly, problems, such as a need to allocate more lead time for design, and greater increased chip area requirements, may arise.
One effective approach to solving such problems is to divide the circuit into modules, each of which is individually designed so as to have a suitable layout. When such a layout is designed, each module has user-designed regions, so that a clock feeding circuit is required for feeding exactly the same clock signal to all of the user-designed regions. Moreover, it is also effective to minimize the clock skew of the entire integrated circuit so as both to shrink the chip area and feed the clock pulse at high speed. This may be performed in two stages. In the first stage, the clock skew for each of the user-designed regions is controlled, and in the second stage, the clock skew among the user-designed regions is controlled. To minimize the clock skew among the user-designed regions, the designer must consider differences in delay time based on differences in interconnection routes from the inputs of the clock pulse to the user-designed regions, the interconnection routes within the respective user-designed regions, the loads of the circuits, the drive responses of the circuits, and the like. At the same time, it is of course desirable to minimize the amount of time spent in the design, including the time for controlling the clock skew.
In a process of wiring large integrated circuits, generally, it is impossible to take into account every factor influencing delay times as described above, so that an accurate delay time is difficult to determine until after the layout design is completed. That is, with a conventional clock feeding circuit, it is impossible to eliminate the differences in delay time of the clock pulse among the user-designed regions, even through the differences in delay time within each such region may be eliminated. Therefore, in a case where the clock feeding circuit is divided among a plurality of the user-designed regions, the differences in delay time of the clock pulse over the entire integrated circuit cannot easily be controlled.